module tb_counter();
    reg load;
    reg clk;
    reg enable;
    wire [3:0] out;
    counter #(4) dut(load, enable, clk, out);
    always
    begin
        clk = 1; #5; clk = 0; #5;
    end
    initial begin
        $dumpfile("tb_counter");
        $dumpvars;
        load = 0;enable = 1;#20;
        load=1;#30;
        load=0;#20;
        load=1;enable=0;#40;
        $finish;
    end
endmodule